This invention relates to computer systems which use non-volatile memories. More particularly, it relates to non-volatile memories which can be erased by erasing blocks, or sectors, of memory cells, rather than just erasing one cell at a time. One type of a non-volatile memory which is block erasable is called a flash EPROM or EEPROM.
Flash EPROMs employing single-transistor memory cells, using hot-carrier injection for programming and Fowler-Nordheim tunnelling for erasure are described, for example, in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90ns 100K Erase/Program Cycle Megabit Flash Memory," V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787, which is incorporated herein by reference.
As the number of cells increases for the same physical size of a silicon chip, such EPROM's are called high density.
For high density flash EPROMs, the trend is towards sectored architecture for arrays so that flash erase can be done on either individual blocks or the complete array.
Erasure in flash EPROM's is generally accomplished by first programing, preconditioning, all the cells in a block of cells, and then erasing all those same cells. This action is taken without regard to whether the block of cells is in an erased state.
Over-erasure is a major problem in flash EPROM devices. If an erased cell receives too many erase pulses, it might go into depletion. Once a memory cell is depleted, it will conduct current even with zero voltage on its gate, and will be hard or even impossible to program due to current sharing by depleted cells on the same column (bitline).
Another problem in flash EPROM devices is low endurance. Endurance refers to the number of times a cell can be programmed or erased before it malfunctions. Currently, flash EPROMs must be erase preconditioned before they can be erased. The number of cycles possible to write and then erase a flash EPROM is limited. When the limit is reached, the memory cell will remain in one state; it can not be switched to a different state.
The erase cycle time has been unnecessarily long because existing erase methods do not discriminate between blocks of cells which need to be preconditioned/erased and those which have already been erased.